1. Field of the Invention:
The present invention relates to a method for forming an interconnection for receiving bumps or balls of a semiconductor device for testing or burn-in of the device. In particular, the present invention relates to a method for forming sloped-wall, metal-lined interconnections to receive and contain portions of solder balls of a semiconductor device therein.
2. State of the Art:
Integrated circuit devices are well-known in the prior art. Such devices, or so-called “semiconductor dice,” may include a large number of active semiconductor components (such as diodes, transistors) in combination with (e.g., in one or more circuits) various passive components (such as capacitors, resistors), all residing on a “semiconductor chip” or die of silicon or, less typically, gallium arsenide or indium phosphide. The combination of components results in a semiconductor or integrated circuit die that performs one or more specific functions, such as a microprocessor die or a memory die, the latter as exemplified by ROM, PROM, EPROM, EEPROM, DRAM and SRAM dice.
Such semiconductor dice are normally designed to be supported or carried in an encapsulant or other package and normally have a plurality of externally-accessible connection elements in the form of solder balls, pins, or leads, to which the circuits on each semiconductor die are electrically connected within the package to access other electronic components employed in combination with each semiconductor die. Bond pads on the active surface of a die may be directly in contact with the connection elements, or connected thereto with intermediate elements, such as bond wires or TAB (Tape Automated Bonding, or flex circuit) connections, or rerouting traces extending to remote locations on the die active surface. An encapsulant is usually a filled polymer compound transfer molded about the semiconductor die to provide mechanical support and environmental protection for the semiconductor die, may incorporate a heat sink in contact with the die, and is normally square or rectangular in shape.
Bare semiconductor dice are usually tested at least for continuity, and often more extensively, during the semiconductor die fabrication process and before packaging. Such more extensive testing may be, and has been, accomplished by placing a bare semiconductor die in a temporary package having terminals aligned with the terminals (bond pads) of the semiconductor die to provide electrical access to the circuits on the semiconductor die and subjecting the semiconductor die via the assembled temporary package to burn-in and discrete testing. Such temporary packages may also be used to test entire semiconductor wafers prior to singulating the semiconductor wafers into individual semiconductor dice. Exemplary state-of-the-art fixtures and temporary packages for semiconductor die testing are disclosed in U.S. Pat. Nos. 5,367,253; 5,519,332; 5,448,165; 5,475,317; 5,468,157; 5,468,158; 5,483,174; 5,451,165; 5,479,105; 5,088,190; and 5,073,117. U.S. Pat. Nos. 5,367,253 and 5,519,332, assigned to the assignee of the present application, are each hereby incorporated herein for all purposes by this reference.
Discrete testing includes testing the semiconductor dice for speed and for errors that may occur after fabrication and after burn-in. Burn-in is a reliability test of a semiconductor die to identify physical and electrical defects that would cause the semiconductor die to fail to perform to specifications or to fail altogether before its normal operational life cycle is reached. Thus, the semiconductor die is subjected to an initial heavy duty cycle that elicits latent silicon defects. Burn-in testing is usually conducted at elevated potentials and for a prolonged period of time, typically 24 hours, at varying and reduced and elevated temperatures, such as −15° C. to 125° C., to accelerate failure mechanisms. Semiconductor dice that survive discrete testing and burn-in are termed “known good die,” or “KGD.”
As noted above, such testing is generally performed on bare semiconductor dice. However, while desirable for saving the cost of encapsulating bad semiconductor dice, testing bare, unpackaged semiconductor dice requires a significant amount of handling of these rather fragile structures. The temporary package must not only be compatible with test and burn-in procedures, but must also physically secure and electrically access the semiconductor die without damaging the semiconductor die. Similarly, alignment and assembly of a semiconductor die within the temporary package and disassembly after testing must be effected without semiconductor die damage. The small size of the semiconductor die itself and minute pitch (spacing) of the bond pads of the semiconductor die, as well as the fragile nature of the thin bond pads and the thin protective layer covering devices and circuit elements on the active surface of the semiconductor die, make this somewhat complex task extremely delicate. Performing these operations at high speeds with requisite accuracy and repeatability has proven beyond the capabilities of most state of the art equipment. Thus, since the encapsulant of a finished semiconductor die provides mechanical support and protection for the semiconductor die, in some instances, it is preferable to test and burn-in semiconductor dice after encapsulation.
A common finished semiconductor die package design is a flip-chip design. A flip-chip semiconductor design comprises a pattern or array of terminations (e.g., bond pads or rerouting trace ends) spaced about an active surface of the semiconductor die for face-down mounting of the semiconductor die to a carrier substrate (such as a printed circuit board, FR4 board, ceramic substrate, or the like). Each termination has a minute solder ball or other conductive connection element disposed thereon for making a connection to a trace end or terminal on the carrier substrate. This arrangement of connection elements is usually referred to as a Ball Grid Array or “BGA.” The flip-chip is attached to the substrate trace ends or terminals, which are arranged in a mirror-image of the BGA, by aligning the BGA thereover and (if solder balls are used) refluxing the solder balls for simultaneous permanent attachment and electrical communication of the semiconductor die to the carrier substrate conductors.
Such flip-chips may be tested and/or burned-in prior to their permanent connection to a carrier substrate by placing each flip-chip in a temporary package, such as those discussed above. As shown in FIG. 31, each solder ball 304 attached to a bond pad 302 of a flip-chip-configured die 300 is in physical contact with a conductive trace 306 on a contact wall 308 of the temporary package. The conductive traces 306 transmit electrical signals to the die 300 for testing or burn-in. With such a temporary package, each solder ball 304 contacts each conductive trace 306 at only one contact point 310. With only one contact point 310 per solder ball 304, all of the stresses caused by biasing the die 300 to the contact wall 308 of the temporary package are concentrated on the one contact point 310 on each solder ball 304. These stresses can result in the solder balls 304 fracturing, dislodging from the bond pad 302, or otherwise damaging the flip-chip-configured die 300.
Furthermore, such a temporary package configuration is also insensitive to ensuring electrical connection to the temporary package of non-spherical/irregularly shaped solder balls, or different sized balls, in the BGA. FIG. 32 illustrates an under-sized solder ball 312 in the arrangement similar to that shown in FIG. 31. Elements common between FIG. 31 and FIG. 32 retain the same designation. The under-sized solder ball 312 does not make contact with the conductive trace 306. This can give a false failure indication for the flip-chip-configured die 300, when, in reality, it could be “good” when an adequate connection is achieved when the under-sized solder ball 312 is refluxed for permanent attachment to a carrier substrate. At the least, the die in question is initially rejected and must be retested to verify the source of the apparent failure.
Therefore, it would be advantageous to develop improved methods and apparatus for use with flip-chip-retaining temporary packages, wherein the temporary packages can compensate for irregular solder ball shape and size, and reduce the risk of damage to the semiconductor device under test.